University of California, Irvine

EECS 170LB

ame: Usman Syed (SID# 88355872)
Date: January 30, 2023
Date and time of performed lab: January 25, 2023 (Wednesday 2:00 PM to 4:50 PM)
Class: EECS 170LB
Lab 2: DC Analysis of MOS Transistors
Introduction:
This lab's goal is to increase our understanding of MOSFETs, especially NMOS and PMOS
transistors. As we will be building MOSFET-based circuits in the application for the first time—
we have only previously dealt with diode circuits—it also serves as an introduction to utilizing
LTSpice. Using the lab manual's illustrations, we will construct five different circuits in
LTSpice, each of which has an NMOS or PMOS transistor. These circuits consist of two current
mirror circuits, a diode connected NMOS circuit, a conventional NMOS circuit, and a standard
PMOS circuit. We will examine the drain current characteristics by performing a DC sweep with
specified voltage or resistance values and analyze the resulting graphs to understand the impact
of each MOSFET configuration.
Part 1 NMOS Transistor:
Vgs from 0 to 20V for different Vds levels (e.g., 1V, 5V, 9V…)This study source was downloaded by 100000878898342 from CourseHero.com on 01-30-2024 23:13:18 GMT -06:00
https://www.coursehero.com/file/189903912/EECS-170LB-LAB2pdf/
Q. Describe the graph, what can you say about the NMOS behavior?
Three curves that represent various VDS levels on the graph show the relationship between
Drain current and VGS. We can see that in this NM