Texas A&M University

ECEN 749  

ECEN749 LAB REPORT OF LAB1

Introduction
In this lab we learned the basic knowledge of the using of ISE by stepping
through a simple example and a simple Verilog program. After finishing the
example, I designed a simple counter and a jackpot game Verilog program
with the knowledge I gained from the examples.
Procedure
1. Following the lab introduction to learn how to create a new design project
an add the source documents.
2. Creating a new project and coding a simple LED program by following the
introduction, then learning how to create the User Constraint File and
learning how to download the program into the FPGA.
3. Designing a Verilog program of a 4-bit counter with three button “UP”,
“DOWN”, “RESET”. And using four LEDS to display the counting number.
And debugging until the program can work successfully on the hardware.
4. Designing a Verilog program of a JACKPOT game with 4 switches and 4
LEDS. And debugging until the program can work successfully on the
hardware.
Results
1. Learned the way of creating a project and adding source documents.
2. Finished the example sample LED program and it run successful on the
FPGA board.
3. Successfully designed a counter program which can work well on the FPGA
board.
4. Successfully designed a JACKPOT game program which can work well on
the FPGA board.
Conclusion
1. The procedure of creating a project is File > New project > Device
Properties > Add sources > Finish
2. It will take very long time to debug the program.
Verilog Files
COUNTER.v
module counter(
input UP, //input an ouput pins
input DOWN,
input CLOCK,
input RESET,
output [3:0] LEDS
);
reg [3:0] COUNT; //save the number to LEDS
reg R_clk1 = 1'b0; // number to divide the clock
reg [31:0] counter = 1'b0;// use for the counter
always@(posedge R_clk1) //use three buttons to control the LEDS
begin
if(RESET == 1) begin
COUNT <=1'b0;
end else if (UP == 1) begin
COUNT <= COUNT + 1; //count up
end else if (DOWN == 1) begin
COUNT <= COUNT - 1; //count down
end
end
always@ ( posedge CLOCK ) //divide the clock to 1HZ
begin
counter <= counter + 1'b1;
if ( counter == 50000000) // overtun the clk1 after 0.5s
begin
R_clk1 <= ~R_clk1;
counter <= 1'b0; //reset the counter
end
end
assign LEDS[3:0] = COUNT[3:0];
endmodule